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PCA9502
8-bit I/O expander with I2C-bus/SPI interface
Rev. 03 -- 13 October 2006 Product data sheet
1. General description
The PCA9502 is an 8-bit I/O expander with I2C-bus/SPI host interface. The device comes in a very small HVQFN24 package, which makes it ideally suitable for hand-held, battery operated applications. The device also supports software reset, which allows the host to reset the device at any time, independent of the hardware reset signal.
2. Features
2.1 General features
I I I I I I I I Selectable I2C-bus or SPI interface 3.3 V or 2.5 V operation Industrial temperature range: -40 C to +85 C Eight programmable I/O pins Software reset Industrial and commercial temperature ranges Available in HVQFN24 package 16 hardware-selectable slave addresses
2.2 I2C-bus features
I I I I Noise filter on SCL/SDA inputs 400 kbit/s (maximum) Compliant with I2C-bus Fast-mode Slave mode only
2.3 SPI features
I 15 Mbit/s maximum speed I Slave mode only I SPI Mode 0
3. Applications
I Factory automation and process control I Portable and battery operated devices I Cellular data devices
NXP Semiconductors
PCA9502
8-bit I/O expander with I2C-bus/SPI interface
4. Ordering information
Table 1. Ordering information Package Name PCA9502BS HVQFN24 Description Version plastic thermal enhanced very thin quad flat package; SOT616-3 no leads; 24 terminals; body 4 x 4 x 0.85 mm Type number
5. Block diagram
VDD
PCA9502
RESET SCL SDA A0 A1 IRQ
1 k (3.3 V) 1.5 k (2.5 V)
GPIO REGISTER I2C-BUS
8
GPIO[7:0]
VDD VDD I2C/SPI
002aab837
VSS
Fig 1. Block diagram of PCA9502 I2C-bus interface
VDD
PCA9502
RESET SCLK CS SO SI IRQ
1 k (3.3 V) 1.5 k (2.5 V)
GPIO REGISTER SPI
8
GPIO[7:0]
VDD I2C/SPI
002aab838
VSS
Fig 2. Block diagram of PCA9502 SPI interface
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PCA9502
8-bit I/O expander with I2C-bus/SPI interface
6. Pinning information
6.1 Pinning
22 VDD 21 GPIO7 20 GPIO6 19 GPIO5 21 GPIO7 20 GPIO6 19 GPIO5 18 GPIO4 17 VSS 16 GPIO3 15 GPIO2 14 GPIO1 13 GPIO0 VSS 10 VDD 11 IRQ 12 7 8 SCLK 9 VSS
002aab840
24 VDD 23 VSS
24 VDD 1 2 3 4 5 6 SO
terminal 1 index area RESET VDD VDD VDD A0 A1 1 2 3 4 5 6
terminal 1 index area 18 GPIO4 17 VSS 16 GPIO3 15 GPIO2 14 GPIO1 13 GPIO0 RESET VDD VDD VSS CS SI
PCA9502BS
PCA9502BS
VSS 10
VDD 11
SCL
SDA
IRQ 12
7
8
n.c.
9
002aab839
Transparent top view
Transparent top view
a. I2C-bus interface Fig 3. Pin configuration for HVQFN24
b. SPI interface
6.2 Pin description
Table 2. Symbol RESET VDD I2C/SPI Pin description Pin 1 Type Description I device hardware reset (active LOW)[1] power supply I2C-bus or SPI interface select. I2C-bus interface is selected if this pin is at logic HIGH. SPI interface is selected if this pin is at logic LOW. SPI chip select or I2C-bus device address select A0. If SPI configuration is selected by I2C/SPI pin, this pin is the SPI chip select pin (Schmitt trigger, active LOW). If I2C-bus configuration is selected by I2C/SPI pin, this pin along with A1 pin allows user to change the device's base address. SPI data input pin or I2C-bus device address select A1. If SPI configuration is selected by I2C/SPI pin, this is the SPI data input pin. If I2C-bus configuration is selected by I2C/SPI pin, this pin along with A0 pin allows user to change the device's base address. To select the device address, please refer to Table 11. SPI data output pin. If SPI configuration is selected by I2C/SPI pin, this is a 3-stateable output pin. If I2C-bus configuration is selected by I2C/SPI pin, this pin function is undefined and must be left as n.c. (not connected). I2C-bus or SPI input clock. I2C-bus data input/output, open-drain if I2C-bus configuration is selected by I2C/SPI pin. If SPI configuration is selected then this pin is an undefined pin and must be connected to VSS.
(c) NXP B.V. 2006. All rights reserved.
2, 3, 11, 22, 24 4 I
CS/A0
5
I
SI/A1
6
I
SO
7
O
SCL/SCLK SDA
8 9
I I/O
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Product data sheet
Rev. 03 -- 13 October 2006
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23 VSS
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PCA9502
8-bit I/O expander with I2C-bus/SPI interface
Pin description ...continued Pin 12 Type Description O Interrupt (open-drain, active LOW). Interrupt is enabled when interrupt sources are enabled in the I/O Interrupt Enable register (IOIntEna). The interrupt condition is the change of state of the input pins. An external resistor (1 k for 3.3 V, 1.5 k for 2.5 V) must be connected between this pin and VDD. programmable I/O pin programmable I/O pin programmable I/O pin programmable I/O pin programmable I/O pin programmable I/O pin programmable I/O pin programmable I/O pin ground The center pad on the back side of the HVQFN24 package is metallic and should be connected to ground on the printed-circuit board.
Table 2. Symbol IRQ
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 VSS VSS
13 14 15 16 18 19 20 21 10, 17, 23 center pad
I/O I/O I/O I/O I/O I/O I/O I/O -
[1]
See Section 7.1 "Hardware reset, Power-On Reset (POR) and software reset"
7. Functional description
The device interfaces to a host through either I2C-bus or SPI interface (selectable through I2C/SPI pin), and provides the host with eight programmable GPIO pins.
7.1 Hardware reset, Power-On Reset (POR) and software reset
These three reset methods are identical and will reset the internal registers as indicated in Table 3. Table 3 summarizes the state of registers after reset.
Table 3. Register I/O direction I/O interrupt enable I/O control Registers after reset Reset state all bits cleared all bits cleared all bits cleared
Table 4 summarizes the state of hardware pins after reset.
Table 4. Signal I/Os IRQ Signals after reset Reset state inputs HIGH by external pull-up
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PCA9502
8-bit I/O expander with I2C-bus/SPI interface
7.2 Interrupts
The PCA9502 has interrupt generation capability. The interrupt enable register (IOIntEna) enables interrupts due to I/O pin change of state, and the IRQ signal in response to an interrupt generation.
8. Register descriptions
The programming combinations for register selection are shown in Table 5.
Table 5. IODir IOState IOIntEna IOControl Table 6. PCA9502 internal registers Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W Register map - read/write properties Read mode I/O pin direction I/O pin states I/O interrupt enable register I/O pins control Write mode I/O pin direction n/a I/O interrupt enable register I/O pins control
Register name
Register Register address General Register Set 0x0A[1] 0x0B[1] 0x0C[1] 0x0D[1] 0x0E[1] IODir IOState IOIntEna reserved
[2]
bit 7 bit 7 bit 7 reserved
[2]
bit 6 bit 6 bit 6 reserved
[2]
bit 5 bit 5 bit 5 reserved
[2]
bit 4 bit 4 bit 4 reserved
[2]
bit 3 bit 3 bit 3 reserved
[2]
bit 2 bit 2 bit 2 reserved
[2]
bit 1 bit 1 bit 1 reserved
[2]
bit 0 bit 0 bit 0 reserved
[2]
R/W R/W R/W
IOControl
reserved
[2]
reserved
[2]
reserved
[2]
reserved
[2]
SReset
reserved
[2]
reserved
[2]
IOLatch
R/W
[1] [2]
Other addresses 0x00 through 0x09, 0x0F are reserved and should not be accessed (read or write). These bits are reserved and should be set to 0.
8.1 Programmable I/O pins Direction register (IODir)
This register is used to program the I/O pins direction. Bit 0 to bit 7 control GPIO0 to GPIO7.
Table 7. Bit 7:0 IODir register (address 0x0A) bit description Symbol IODir Description set GPIO pins 7:0 to input or output 0 = input 1 = output
Remark: If there is a pending input (GPIO) interrupt and IODir is written, this pending interrupt will be cleared, that is, the interrupt signal will be negated.
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PCA9502
8-bit I/O expander with I2C-bus/SPI interface
8.2 Programmable I/O pins State register (IOState)
When `read', this register returns the actual state of all I/O pins. When `write', each register bit will be transferred to the corresponding IO pin programmed as output.
Table 8. Bit 7:0 IOState register (address 0x0B) bit description Symbol IOState Description Write this register: set the logic level on the output pins 0 = set output pin to zero 1 = set output pin to one Read this register: return states of all pins
8.3 I/O Interrupt Enable register (IOIntEna)
This register enables the interrupt due to a change in the I/O configured as inputs.
Table 9. Bit 7:0 IOIntEna register (address 0x0C) bit description Symbol IOIntEna Description input interrupt enable 0 = a change in the input pin will not generate an interrupt 1 = a change in the input will generate an interrupt
8.4 I/O Control register (IOControl)
Table 10. Bit 7:4 3 IOControl register (address 0x0E) bit description Symbol SReset Description reserved for future use software reset A write to this bit will reset the device. Once the device is reset this bit is automatically set to 0. 2:1 0 IOLatch reserved for future use enable/disable inputs latching 0 = input values are not latched. A change in any input generates an interrupt. A read of the input register clears the interrupt. If the input goes back to its initial logic state before the input register is read, then the interrupt is cleared. 1 = input values are latched. A change in the input generates an interrupt and the input logic value is loaded in the bit of the corresponding input state register (IOState). A read of the IOState register clears the interrupt. If the input pin goes back to its initial logic state before the interrupt register is read, then the interrupt is not cleared and the corresponding bit of the IOState register keeps the logic value that initiates the interrupt. Example: If GPIO4 input was as logic 0 and the input goes to logic 1 then back to logic 0, the IOState register will capture this change and an interrupt is generated (if enabled). When the read is performed on the IOState register, the interrupt is de-asserted, assuming there were no additional input(s) that changed, and bit 4 of the IOState register will read `1'. The next read of the IOState register should now read `0'.
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PCA9502
8-bit I/O expander with I2C-bus/SPI interface
9. I2C-bus operation
The two lines of the I2C-bus are a serial data line (SDA) and a serial clock line (SCL). Both lines are connected to a positive supply via a pull-up resistor, and remain HIGH when the bus is not busy. Each device is recognized by a unique address whether it is a microcomputer, LCD driver, memory or keyboard interface and can operate as either a transmitter or receiver, depending on the function of the device. A device generating a message or data is a transmitter, and a device receiving the message or data is a receiver. Obviously, a passive function like an LCD driver could only be a receiver, while a microcontroller or a memory can both transmit and receive data.
9.1 Data transfers
One data bit is transferred during each clock pulse (see Figure 4). The data on the SDA line must remain stable during the HIGH period of the clock pulse in order to be valid. Changes in the data line at this time will be interpreted as control signals. A HIGH-to-LOW transition of the data line (SDA) while the clock signal (SCL) is HIGH indicates a START condition, and a LOW-to-HIGH transition of the SDA while SCL is HIGH defines a STOP condition (see Figure 5). The bus is considered to be busy after the START condition and free again at a certain time interval after the STOP condition. The START and STOP conditions are always generated by the master.
SDA
SCL data line stable; data valid change of data allowed
mba607
Fig 4. Bit transfer on the I2C-bus
SDA
SDA
SCL S START condition P STOP condition
SCL
mba608
Fig 5. START and STOP conditions
The number of data bytes transferred between the START and STOP condition from transmitter to receiver is not limited. Each byte, which must be eight bits long, is transferred serially with the most significant bit first, and is followed by an acknowledge bit. (see Figure 6). The clock pulse related to the acknowledge bit is generated by the master. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, while the transmitting device releases this pulse (see Figure 7).
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PCA9502
8-bit I/O expander with I2C-bus/SPI interface
acknowledgement signal from receiver SDA MSB
SCL
S START condition
0
1
6
7
8 ACK
0
1
2 to 7
8 ACK
P STOP condition
002aab012
byte complete, interrupt within receiver
clock line held LOW while interrupt is serviced
Fig 6. Data transfer on the I2C-bus
data output by transmitter
transmitter stays off of the bus during the acknowledge clock
data output by receiver
acknowledgement signal from receiver
SCL from master
S START condition
0
1
6
7
8
002aab013
Fig 7. Acknowledge on the I2C-bus
A slave receiver must generate an acknowledge after the reception of each byte, and a master must generate one after the reception of each byte clocked out of the slave transmitter. There is an exception to the `acknowledge after every byte' rule. It occurs when a master is a receiver: it must signal an end of data to the transmitter by not signalling an acknowledge on the last byte that has been clocked out of the slave. The acknowledge related clock, generated by the master should still take place, but the SDA line will not be pulled down. In order to indicate that this is an active and intentional lack of acknowledgement, we shall term this special condition as a `negative acknowledge'.
9.2 Addressing and transfer formats
Each device on the bus has its own unique address. Before any data is transmitted on the bus, the master transmits on the bus the address of the slave to be accessed for this transaction. A well-behaved slave with a matching address, if it exists on the network, should of course acknowledge the master's addressing. The addressing is done by the first byte transmitted by the master after the START condition. An address on the network is seven bits long, appearing as the most significant bits of the address byte. The last bit is a direction (R/W) bit. A `0' indicates that the master is transmitting (write) and a `1' indicates that the master requests data (read). A complete data transfer, comprised of an address byte indicating a `write' and two data bytes is shown in Figure 8.
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PCA9502
8-bit I/O expander with I2C-bus/SPI interface
SDA
SCL
S START condition
0 to 6 address
7 R/W
8 ACK
0 to 6 data
7
8 ACK
0 to 6 data
7
8 ACK
P STOP condition
002aab046
Fig 8. A complete data transfer
When an address is sent, each device in the system compares the first seven bits after the START with its own address. If there is a match, the device will consider itself addressed by the master, and will send an acknowledge. The device could also determine if in this transaction it is assigned the role of a slave receiver or slave transmitter, depending on the R/W bit. Each node of the I2C-bus network has a unique seven-bit address. The address of a microcontroller is of course fully programmable, while peripheral devices usually have fixed and programmable address portions. When the master is communicating with one device only, data transfers follow the format of Figure 8, where the R/W bit could indicate either direction. After completing the transfer and issuing a STOP condition, if a master would like to address some other device on the network, it could start another transaction by issuing a new START. Another way for a master to communicate with several different devices would be by using a `repeated START'. After the last byte of the transaction was transferred, including its acknowledge (or negative acknowledge), the master issues another START, followed by address byte and data, without effecting a STOP. The master may communicate with a number of different devices, combining `reads' and `writes'. After the last transfer takes place, the master issues a STOP and releases the bus. Possible data formats are demonstrated in Figure 9. Note that the repeated START allows for both change of a slave and a change of direction, without releasing the bus. We shall see later on that the change of direction feature can come in handy even when dealing with a single device. In a single master system, the repeated START mechanism may be more efficient than terminating each transfer with a STOP and starting again. In a multimaster environment, the determination of which format is more efficient could be more complicated, as when a master is using repeated STARTs it occupies the bus for a long time and thus preventing other devices from initiating transfers.
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PCA9502
8-bit I/O expander with I2C-bus/SPI interface
data transferred (n bytes + acknowledge) master write: S SLAVE ADDRESS W A DATA A DATA A P
START condition
write
acknowledge
acknowledge
acknowledge STOP condition
data transferred (n bytes + acknowledge) master read: S SLAVE ADDRESS R A DATA A DATA NA P
START condition
read
acknowledge
acknowledge
not acknowledge STOP condition
data transferred (n bytes + acknowledge) combined formats: S SLAVE ADDRESS R/W A DATA A Sr SLAVE ADDRESS R/W A
data transferred (n bytes + acknowledge) DATA A P
START condition
read or write
acknowledge
acknowledge
repeated START condition
read or write
acknowledge
acknowledge STOP condition
002aab458
direction of transfer may change at this point
Fig 9. I2C-bus data formats
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8-bit I/O expander with I2C-bus/SPI interface
9.3 Addressing
Before any data is transmitted or received, the master must send the address of the receiver via the SDA line. The first byte after the START condition carries the address of the slave device and the read/write bit. Table 11 shows how the PCA9502's address can be selected by using A1 and A0 pins. For example, if these 2 pins are connected to VDD, then the PCA9502's address is set to 0x90, and the master communicates with it through this address.
Table 11. A1 VDD VDD VDD VDD VSS VSS VSS VSS SCL SCL SCL SCL SDA SDA SDA SDA
[1]
PCA9502 address map A0 VDD VSS SCL SDA VDD VSS SCL SDA VDD VSS SCL SDA VDD VSS SCL SDA PCA9502 I2C-bus addresses (hex)[1] 0x90 (1001 000X) 0x92 (1001 001X) 0x94 (1001 010X) 0x96 (1001 011X) 0x98 (1001 100X) 0x9A (1001 101X) 0x9C (1001 110X) 0x9E (1001 111X) 0xA0 (1010 000X) 0xA2 (1010 001X) 0xA4 (1010 010X) 0xA6 (1010 011X) 0xA8 (1010 100X) 0xAA (1010 101X) 0xAC (1010 110X) 0xAE (1010 111X)
X = logic 0 for write cycle; X = logic 1 for read cycle.
9.4 Use of sub-addresses
When a master communicates with the PCA9502 it must send a sub-address in the byte following the slave address byte. This sub-address is the internal address of the word the master wants to access for a single byte transfer, or the beginning of a sequence of locations for a multi-byte transfer. A sub-address is an 8-bit byte. Unlike the device address, it does not contain a direction (R/W) bit, and like any byte transferred on the bus it must be followed by an acknowledge. A register write cycle is shown in Figure 10. The START is followed by a slave address byte with the direction bit set to `write', a sub-address byte, a number of data bytes, and a STOP signal. The sub-address indicates which register the master wants to access. and the data bytes which follow will be written one after the other to the sub-address location.
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PCA9502
8-bit I/O expander with I2C-bus/SPI interface
S
SLAVE ADDRESS
W
A
REGISTER ADDRESS
A
nDATA
A
P
002aab047
White block: host to PCA9502 Grey block: PCA9502 to host
Fig 10. Master writes to slave
The register read cycle (see Figure 11) commences in a similar manner, with the master sending a slave address with the direction bit set to `write' with a following sub-address. Then, in order to reverse the direction of the transfer, the master issues a repeated START followed again by the device address, but this time with the direction bit set to `read'. The data bytes starting at the internal sub-address will be clocked out of the device, each followed by a master-generated acknowledge. The last byte of the read cycle will be followed by a negative acknowledge, signalling the end of transfer. The cycle is terminated by a STOP signal.
S
SLAVE ADDRESS
W
A
REGISTER ADDRESS
A
S
SLAVE ADDRESS
R
A
nDATA
A
LAST DATA
NA
P
002aab048
White block: host to PCA9502 Grey block: PCA9502 to host
Fig 11. Master read from Slave Table 12. Bit 7 6:3 2:1 0 Register address byte (I2C-bus) Name A[3:0] Function not used internal register select not used, set to 0 not used
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8-bit I/O expander with I2C-bus/SPI interface
10. SPI operation
SCLK SI R/W A3 A2 A1 A0 0 0 X D7 D6 D5 D4 D3 D2 D1 D0
002aab925
R/W = 0; A[3:0] = register address
a. Register write
SCLK SI SO R/W A3 A2 A1 A0 0 0 X D7 D6 D5 D4 D3 D2 D1 D0
002aab926
R/W = 1; A[3:0] = register address
b. Register read Fig 12. SPI operation Table 13. Bit 7 6:3 2:1 0 Register address byte (SPI) Name R/W A[3:0] Function 1: read from PCA9502 0: write to PCA9502 internal register select not used, set to 0 not used
11. Limiting values
Table 14. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD VI II IO Ptot P/out Tamb Tstg
[1]
Parameter supply voltage input voltage input current output current total power dissipation power dissipation per output ambient temperature storage temperature
Conditions any input any input any output
Min -0.3 -0.3 -10 -10 -40 -65
Max +4.6 +5.5[1] +10 +10 300 50 +85 +150
Unit V V mA mA mW mW C C
5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 4.6 V steady state voltage tolerance on inputs and outputs when no supply voltage is present.
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8-bit I/O expander with I2C-bus/SPI interface
12. Static characteristics
Table 15. Static characteristics VDD = (2.5 V 0.2 V) or (3.3 V 0.3 V); Tamb = -40 C to +85 C; unless otherwise specified. Symbol Supplies VDD IDD supply voltage supply current operating; no load static; no load Inputs I2C/SPI VIH VIL IL Ci Output SO VOH VOL Co VIH VIL VOH VOL IL Co VOL Co I2C-bus VIH VIL VOL IL Co HIGH-level output voltage LOW-level output voltage output capacitance HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage leakage current output capacitance LOW-level output voltage output capacitance input/output SDA HIGH-level input voltage LOW-level input voltage LOW-level output voltage leakage current output capacitance IOL = 1.6 mA IOL = 4 mA input; VI = 0 V or 5.5 V[1] 1.6 5.5[1] 0.6 0.4 10 7 2.0 5.5[1] 0.8 0.4 10 7 V V V V A pF IOL = 1.6 mA IOL = 4 mA IOH = -400 A IOH = -4 mA IOL = 1.6 mA IOL = 4 mA input; VI = 0 V or 5.5 V[1] IOH = -400 A IOH = -4 mA IOL = 1.6 mA IOL = 4 mA Inputs/outputs GPIO0 to GPIO7 1.6 1.85 5.5[1] 0.6 0.4 1 4 0.4 4 2.0 2.4 5.5[1] 0.8 0.4 1 4 0.4 4 V V V V V V A pF V V pF 1.85 0.4 4 2.4 0.4 4 V V V V pF HIGH-level input voltage LOW-level input voltage leakage current input capacitance input; VI = 0 V or 5.5 V[1] 1.6 5.5[1] 0.6 1 3 2.0 5.5[1] 0.8 1 3 V V A pF 2.3 2.7 750 600 3.0 3.6 750 600 V A A Parameter Conditions VDD = 2.5 V Min Max VDD = 3.3 V Min Max Unit
Output IRQ
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8-bit I/O expander with I2C-bus/SPI interface
Table 15. Static characteristics ...continued VDD = (2.5 V 0.2 V) or (3.3 V 0.3 V); Tamb = -40 C to +85 C; unless otherwise specified. Symbol I2C-bus VIH VIL IL Ci
[1]
Parameter inputs SCL, CS/A0, SI/A1 HIGH-level input voltage LOW-level input voltage leakage current input capacitance
Conditions
VDD = 2.5 V Min 1.6 Max 5.5[1] 0.6 10 7
VDD = 3.3 V Min 2.0 Max 5.5[1] 0.8 10 7
Unit
V V A pF
input; VI = 0 V or 5.5 V[1]
-
5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 3.8 V steady state voltage tolerance on inputs and outputs when no supply voltage is present.
13. Dynamic characteristics
Table 16. I2C-bus timing specifications All the timing limits are valid within the operating supply voltage, ambient temperature range and output load; VDD = (2.5 V 0.2 V) or (3.3 V 0.3 V); Tamb = -40 C to +85 C; refer to VIL and VIH with an input voltage of VSS to VDD. All output load = 25 pF, except SDA output load = 400 pF.[1] Symbol Parameter Conditions Standard-mode I2C-bus Min fSCL tBUF tHD;STA tSU;STA tSU;STO tHD;DAT tVD;ACK tVD;DAT tSU;DAT tLOW tHIGH tf tr tSP td1 td4 td5
[1] [2]
Fast-mode I2C-bus Min 0 1.3 0.6 0.6 0.6 0 150 1.3 0.6 0.5 0.2 0.2 Max 400 0.6 0.6 300 300 50 -
Unit
Max 100 0.6 0.6 300 1000 50 -
SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition set-up time for a repeated START condition set-up time for STOP condition data hold time data valid acknowledge time data valid time data set-up time LOW period of the SCL clock HIGH period of the SCL clock fall time of both SDA and SCL signals rise time of both SDA and SCL signals pulse width of spikes that must be suppressed by the input filter I2C-bus GPIO output valid time I2C input pin interrupt valid time I2C input pin interrupt clear time SCL LOW to data out valid
[2]
0 4.7 4.0 4.7 4.7 0 250 4.7 4.0 0.5 0.2 0.2
kHz s s s s ns s ns ns s s ns ns ns s s s
A detailed description of the I2C-bus specification, with applications, is given in brochure "The I2C-bus and how to use it". This brochure may be ordered using the code 9398 393 40011. Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if SDA is held LOW for a minimum of 25 ms.
PCA9502_3
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Product data sheet
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PCA9502
8-bit I/O expander with I2C-bus/SPI interface
protocol
START condition (S) tSU;STA
bit 7 MSB (A7) tLOW tHIGH
bit 6 (A6)
bit 0 LSB (R/W)
acknowledge (A)
STOP condition (P)
1/f
SCL
SCL tBUF tr tf tSP
SDA
tHD;STA
tSU;DAT
tHD;DAT
tVD;DAT
tVD;ACK
tSU;STO
002aab489
Rise and fall times refer to VIL and VIH.
Fig 13. I2C-bus timing diagram
SDA
SLAVE ADDRESS
W
A
A IOSTATE REG.
A
DATA td1
A
GPIOn
002aab255
Fig 14. Write to output
ACK from slave SDA SLAVE ADDRESS W A A IOSTATE REG. A S
ACK from slave SLAVE ADDRESS R A
ACK from master DATA A P
IRQ td4 GPIOn td5
002aab877
Fig 15. GPIO pin interrupt
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Product data sheet
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NXP Semiconductors
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8-bit I/O expander with I2C-bus/SPI interface
Table 17. SPI-bus timing specifications All the timing limits are valid within the operating supply voltage, ambient temperature range and output load; VDD = (2.5 V 0.2 V) or (3.3 V 0.3 V); Tamb = -40 C to +85 C; and refer to VIL and VIH with an input voltage of VSS to VDD. All output load = 25 pF, unless otherwise specified. Symbol td(CS_NH-SOZ) tsu(CS_N-SCLK) th(CS_N-SCLK) td(SCLK-SO) tsu(SI-SCLK) th(SI-SCLK) TSCLK tSCLKH tSCLKL tw(CS_NH) td9 td13 Parameter CS HIGH to SO 3-state delay time CS to SCLK setup time CS to SCLK hold time SCLK fall to SO valid delay time SI to SCLK setup time SI to SCLK hold time SCLK period SCLK HIGH time SCLK LOW time CS HIGH pulse width SPI output data valid time SPI interrupt clear time tSCLKL + tSCLKL CL = 100 pF Conditions CL = 100 pF VDD = 2.5 V Min 100 20 10 10 83 30 30 200 200 200 Max 100 25 VDD = 3.3 V Min 100 20 20 10 67 25 25 200 200 200 Max 100 20 ns ns ns ns ns ns ns ns ns ns ns ns Unit
CS th(CS_N-SCLK) tsu(CS_N-SCLK) tSCLKL tSCLKH tw(CS_NH)
th(CS_N-SCLK)
SCLK th(SI-SCLK) tsu(SI-SCLK) SI td(SCLK-SO) SO
002aac429
td(CS_N-SOZ)
Fig 16. Detailed SPI-bus timing
CS SCLK SI GPIOn
002aab878
R/W
A3
A2
A1
A0
0
0
X
D7
D6
D5
D4
D3
D2
D1
D0 td9
R/W = 0; A[3:0] = IOState (0x0B)
Fig 17. SPI write IOState to GPIO switch
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Product data sheet
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NXP Semiconductors
PCA9502
8-bit I/O expander with I2C-bus/SPI interface
CS SCLK SI SO td13 IRQ
002aab879
R/W
A3
A2
A1
A0
0
0
X D7 D6 D5 D4 D3 D2 D1 D0
R/W = 1; A[3:0] = IOState (0x0B)
Fig 18. Read IOState to clear GPIO INT
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Product data sheet
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PCA9502
8-bit I/O expander with I2C-bus/SPI interface
14. Package outline
HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm
SOT616-3
D
B
A
terminal 1 index area A A1 E c
detail X
e1
1/2 e
C b 12 vMCAB wMC 13 y1 C y
e 7 L 6
e
Eh
1/2 e
e2
1 18 terminal 1 index area
24 Dh 0
19 X 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 4.1 3.9 Dh 2.75 2.45 E (1) 4.1 3.9 Eh 2.75 2.45 e 0.5 e1 2.5 e2 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT616-3 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 04-11-19 05-03-10
Fig 19. Package outline SOT616-3 (HVQFN24)
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Product data sheet
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PCA9502
8-bit I/O expander with I2C-bus/SPI interface
15. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling integrated circuits.
16. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
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Product data sheet
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PCA9502
8-bit I/O expander with I2C-bus/SPI interface
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities 16.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 20) than a PbSn process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 18 and 19
Table 18. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 19. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 20.
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Product data sheet
Rev. 03 -- 13 October 2006
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PCA9502
8-bit I/O expander with I2C-bus/SPI interface
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 20. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
17. Abbreviations
Table 20. Acronym GPIO I2C-bus I/O LCD POR SPI Abbreviations Description General Purpose Input/Output Inter Integrated Circuit bus Input/Output Liquid Crystal Display Power-On Reset Serial Peripheral Interface
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Product data sheet
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PCA9502
8-bit I/O expander with I2C-bus/SPI interface
18. Revision history
Table 21. Revision history Release date 20061013 Data sheet status Product data sheet Change notice Supersedes PCA9502_2 Document ID PCA9502_3 Modifications:
* * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Table 15 "Static characteristics", sub-section "Supplies": - IDD, supply current, operating; no load: changed maximum limit from 6.0 mA to 750 A for both 2.5 V and 3.3 V supply voltage ranges - IDD, supply current: added "static; no load" Conditions (max 600 A)
PCA9502_2 PCA9502_1
20060803 20060707
Product data sheet Product data sheet
-
PCA9502_1 -
PCA9502_3
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Product data sheet
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PCA9502
8-bit I/O expander with I2C-bus/SPI interface
19. Legal information
19.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
19.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
20. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
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Product data sheet
Rev. 03 -- 13 October 2006
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8-bit I/O expander with I2C-bus/SPI interface
21. Contents
1 2 2.1 2.2 2.3 3 4 5 6 6.1 6.2 7 7.1 7.2 8 8.1 8.2 8.3 8.4 9 9.1 9.2 9.3 9.4 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 19 19.1 19.2 19.3 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General features . . . . . . . . . . . . . . . . . . . . . . . . 1 I2C-bus features . . . . . . . . . . . . . . . . . . . . . . . . 1 SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Hardware reset, Power-On Reset (POR) and software reset . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Register descriptions . . . . . . . . . . . . . . . . . . . . 5 Programmable I/O pins Direction register (IODir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Programmable I/O pins State register (IOState) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 I/O Interrupt Enable register (IOIntEna) . . . . . . 6 I/O Control register (IOControl). . . . . . . . . . . . . 6 2C-bus operation . . . . . . . . . . . . . . . . . . . . . . . . 7 I Data transfers . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Addressing and transfer formats. . . . . . . . . . . . 8 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Use of sub-addresses. . . . . . . . . . . . . . . . . . . 11 SPI operation . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13 Static characteristics. . . . . . . . . . . . . . . . . . . . 14 Dynamic characteristics . . . . . . . . . . . . . . . . . 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19 Handling information. . . . . . . . . . . . . . . . . . . . 20 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Introduction to soldering . . . . . . . . . . . . . . . . . 20 Wave and reflow soldering . . . . . . . . . . . . . . . 20 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 20 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 21 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 23 Legal information. . . . . . . . . . . . . . . . . . . . . . . 24 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 24 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 19.4 20 21 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Contact information . . . . . . . . . . . . . . . . . . . . 24 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2006.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 13 October 2006 Document identifier: PCA9502_3

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